GRLIB=.
TOP=leon3mp
BOARD=actel-coremp7-1000

DEVICE=M1AFS1500
EFFORT=high
SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
SDC=leon3mp.sdc
PDC=leon3mp.pdc
CLEAN=soft-clean
TECHLIBS = fusion

# tools
DESIGNER = designer
SYNPLIFY = synplify
PRECISION = precision

SRCS := $(wildcard *.vhd)

##################  project specific targets ##########################

all : leon3mp.pdb

synplify-launch: $(TOP)_synplify.prj
	$(SYNPLIFY) $(TOP)_synplify.prj&
	-@mkdir synplify>& tmp.err; touch synplify/dummy.mif
	-@mv synplify/*.mif .

actel-syn: $(TOP)_synplify.prj synplify/$(TOP).edf $(TOP)_designer.tcl
	-mkdir ./actel
	$(DESIGNER) script:$(TOP)_designer.tcl
	
actel-pre: precision/impl1/$(TOP).edf $(TOP)_designer_pre.tcl
	-mkdir ./actel
	$(DESIGNER) script:$(TOP)_designer_pre.tcl	

actel-launch: $(TOP)_synplify.prj synplify/$(TOP).edf $(TOP)_designer.tcl $(TOP).adb
	$(DESIGNER) $(TOP).adb &
	
precision-launch: 
	$(PRECISION) -file $(TOP)_precision.tcl
	
precision: $(TOP)_precision.tcl $(SRCS)
	$(PRECISION) -shell -file $(TOP)_precision.tcl
	
leon3mp.pdb : $(TOP)_precision.tcl $(SRCS) $(TOP)_designer.tcl
	$(PRECISION) -shell -file $(TOP)_precision.tcl
	$(DESIGNER) script:$(TOP)_designer_pre.tcl
	